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Highly Efficient Sparse Neural Network Computing: Hardware and Software Solutions.

, , , , , , and . FPGA, page 121. ACM, (2019)

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Stereo Correspondence Using Stripe Adjacency Graph., and . ICPR (1), page 123-126. IEEE Computer Society, (2006)An ultra low power operated logic NVM for passive UHF RFID tag applications., , , , , and . ICICDT, page 1-4. IEEE, (2016)FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits., and . DAC, page 644-649. ACM Press, (1997)Latency Minimal Scheduling with Maximum Instruction Parallelism., , and . ASICON, page 1-4. IEEE, (2019)Blockchain-Based Interpretable Electric Vehicle Battery Life Prediction in IoV., , , , , and . IEEE Internet Things J., 11 (4): 7214-7227 (February 2024)Global priors guided modulation network for joint super-resolution and SDRTV-to-HDRTV., , , , , and . Neurocomputing, (October 2023)A Model-driven Early Warning Approach for Transmission Lines Failure under Wind Storms., , , , , , and . iSPEC, page 1-5. IEEE, (2023)AQM-based Buffer Delay Guarantee for Congestion Control in 5G Networks., , , , and . WCNC, page 1-6. IEEE, (2023)A General-Purpose Compiler Design for Instruction-Based AI Accelerator Implementation., , and . ASICON, page 1-4. IEEE, (2023)Highly Efficient Modulo Loop Pipeline For High Level Synthesis., , and . ASICON, page 1-4. IEEE, (2021)