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Disambiguation of "Bagherzadeh, Nader"

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ADVOCAT: Automated deadlock verification for on-chip cache coherence and interconnects.

, , , and . DATE, page 1640-1645. IEEE, (2016)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hassan Bagherzadeh

Faramarz Nader

Nader Tawassoli

Nader Purnaqchéband

Nader Ahmad

 

Other publications of authors with the same name

Multiple Branch and Block Prediction., and . HPCA, page 94-103. IEEE Computer Society, (1997)Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost., , and . ASP-DAC, page 872-877. IEEE Computer Society, (2007)Partition Pruning: Parallelization-Aware Pruning for Dense Neural Networks., , , and . PDP, page 307-311. IEEE, (2020)Flow mapping and data distribution on mesh-based deep learning accelerator., , , , and . NOCS, page 13:1-13:8. ACM, (2019)A Multi-Standard Viterbi Decoder for Mobile Applications Using a Reconfigurable Architecture., , and . VTC Fall, page 1-5. IEEE, (2006)A scalable delay insensitive asynchronous NoC with adaptive routing., , and . ICT, page 995-1002. IEEE, (2010)Persepolis: Recovering history with a handheld camera., , , and . Eurographics (Posters), Eurographics Association, (2003)Power and Performance Optimal NoC Design for CPU-GPU Architecture Using Formal Models., and . DATE, page 634-637. IEEE, (2019)Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic., , , and . IET Circuits Devices Syst., 9 (5): 343-352 (2015)Scalable load balancing congestion-aware Network-on-Chip router architecture., , and . J. Comput. Syst. Sci., 79 (4): 421-439 (2013)