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Disambiguation of "Pandey, Sujan"

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Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs.

, and . DATE, page 206-211. ACM, (2008)

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Sujan Pandey

Sujan Rajbhandari

Shantanu Pandey

Mark-Alexander Sujan

Dharmendra Pandey

 

Other publications of authors with the same name

Transient errors resiliency analysis technique for automotive safety critical applications., and . DATE, page 1-4. European Design and Automation Association, (2014)Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis., , and . VLSI-SoC, page 296-301. IEEE, (2006)Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture., , and . VLSI-SoC, page 222-227. IEEE, (2006)Soft-errors resilient logic optimization for low power., and . IOLTS, page 19-24. IEEE Computer Society, (2012)Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters., , , , and . VLSI-SoC, page 302-307. IEEE, (2006)Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique., and . ISCAS, IEEE, (2006)Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint., and . DAC, page 663-668. ACM, (2006)On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects., , , , and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 242-254. Springer, (2007)Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip., , and . ReCoSoC, page 85-92. Univ. Montpellier II, (2005)Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture., and . FPL, page 1-6. IEEE, (2006)