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A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (6): 1132-1140 (2021)

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A technique to suppress tail current flicker noise in CMOS LC VCOs., , , and . ISCAS, IEEE, (2006)Design and optimization of a high PSRR CMOS bandgap voltage reference., , , and . ISCAS (1), page 45-48. IEEE, (2004)A compact, low power, fully integrated clock frequency doubler., , and . ICECS, page 563-566. IEEE, (2003)Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators., , , and . ISCAS, page 157-160. IEEE, (2015)A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology., , , , and . APCCAS, page 21-24. IEEE, (2008)A Power-Efficient Clock and Data Recovery Circuit in 0.18 µm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication., , and . IEEE J. Solid State Circuits, 42 (10): 2235-2244 (2007)Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications., , , and . IEEE J. Solid State Circuits, 43 (7): 1699-1710 (2008)A low-power CMOS Gm-C filter for wireless receiver applications with on-chip automatic tuning system., , , , and . ISCAS, IEEE, (2006)Design Flow to Develop Wideband Inverter-Based Circuits Using C/ID Methodology., , and . SMACD, page 1-4. IEEE, (2023)Optimal PAM Order for Wireline Communication., , and . ISCAS, page 1-5. IEEE, (2021)