Author of the publication

Fast inter-prediction algorithms for spatial Scalable High efficiency Video Coding SHVC.

, , , and . Signal Image Video Process., 13 (1): 145-153 (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Perceptual Evaluation of JPEG2000., , , and . Eur. Trans. Telecommun., 15 (2): 135-143 (2004)Fast inter-prediction algorithms for spatial Scalable High efficiency Video Coding SHVC., , , and . Signal Image Video Process., 13 (1): 145-153 (2019)Fast coding unit partitioning method based on edge detection for HEVC intra-coding., , , and . Signal Image Video Process., 10 (5): 811-818 (2016)Hardware Design and Implementation of Adaptive Multiple Transforms for the Versatile Video Coding Standard., , , , and . IEEE Trans. Consumer Electronics, 64 (4): 424-432 (2018)Analysis of Coding and Transfer of Arien Video Sequences from H.264 Standard., , , and . ATSIP, page 1-5. IEEE, (2020)Real-time H.264/AVC baseline decoder implementation on TMS320C6416., , , , and . J. Real-Time Image Processing, 7 (4): 215-232 (2012)Fast coding unit selection and motion estimation algorithm based on early detection of zero block quantified transform coefficients for high-efficiency video coding standard., , , and . IET Image Processing, 10 (5): 371-380 (2016)Analysis and Optimization of UB Video's H.264 Baseline Encoder Implementation on Texas Instruments' TMS320DM642 DSP., , , and . ICIP, page 3277-3280. IEEE, (2006)Optimization and Implementation on Fpga of the DCT/IDCT Algorithm., , , , , and . ICASSP (3), page 928-931. IEEE, (2006)An optimized hardware architecture of 4×4, 8×8, 16×16 and 32×32 inverse transform for HEVC., , , and . ATSIP, page 264-267. IEEE, (2016)