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Disambiguation of "Stechele, Walter"

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A Coprocessor for Accelerating Visual Information Processing.

, , , and . DATE, page 26-31. IEEE Computer Society, (2005)

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Walter Stechele

Walter Stechele

Walter Stechele

Max Stechele

Max Stechele

 

Other publications of authors with the same name

Exploiting Metal Layer Characteristics for Low-Power Routing., , and . PATMOS, volume 2451 of Lecture Notes in Computer Science, page 55-64. Springer, (2002)Pruning CNNs for LiDAR-based Perception in Resource Constrained Environments., , , , , , , , and . IV Workshops, page 228-235. IEEE, (2021)Binary-LoRAX: Low-Latency Runtime Adaptable XNOR Classifier for Semi-Autonomous Grasping with Prosthetic Hands., , , , , , , , , and 2 other author(s). ICRA, page 13430-13437. IEEE, (2021)Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro., , and . ARCS Workshops, volume P-81 of LNI, page 122-131. GI, (2006)Design of fine-grained sequential approximate circuits using probability-aware fault emulation., and . ISLPED, page 73-78. IEEE, (2015)Towards low-cost fault detection strategy of FPGA configuration memory in real-time systems., , and . IOLTS, page 81-86. IEEE, (2014)Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems., , , and . ARC, volume 5992 of Lecture Notes in Computer Science, page 55-67. Springer, (2010)Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources., , , and . FPL, page 75-82. IEEE, (2012)Efficient power modeling techniques for combinational and sequential RTL macroblocks., and . ICECS, page 705-708. IEEE, (2002)Impact of technology evolution on dual supply voltage scaling and gate resizing in power-driven logic synthesis., , , and . ICECS, page 697-700. IEEE, (2002)