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Disambiguation of "Louërat, Marie-Minerve"

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Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology.

, , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (12): 2323-2333 (2016)

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Martin Marienburg

Charlotte Marien

Wolfgang Marienfeld

Karl-Heinz Marien

Rainer Marien

 

Other publications of authors with the same name

Simulation-based hierarchical sizing and biasing of analog firm IPs., , and . BMAS, page 43-48. IEEE, (2009)Background analog and mixed signal calibration system for time-interleaved ADC., , and . Microelectron. J., 46 (7): 656-667 (2015)Switch sizing for very low-voltage switched-capacitor circuits., , and . ICECS, page 1549-1552. IEEE, (2001)Pre-simulation symbolic analysis of synchronization issues between discrete event and timed data flow models of computation., , , , , and . DATE, page 1671-1676. ACM, (2015)Background time skew calibration for time-interleaved ADC using phase detection method., , , and . NEWCAS, page 257-260. IEEE, (2012)Optimizing Resistances and Capacitances of a Continuous-Time ΣΔ ADC., , and . ICECS, page 419-422. IEEE, (2006)Design of a 4th-Order Feed-Forward-Compensated Operational Amplifier for Multi-GHz Sampling Frequency Continuous-Time Bandpass Sigma-Delta Modulators., , and . ISCAS, page 1-5. IEEE, (2019)Split ADC digital background calibration for high speed SHA-less pipeline ADCs., , , and . ISCAS, page 1143-1146. IEEE, (2014)Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP., , , , and . DATE, page 282-285. IEEE, (2020)Breaking Analog Biasing Locking Techniques via Re-Synthesis., , , and . ASP-DAC, page 555-560. ACM, (2021)