Author of the publication

Guest Editorial: IEEE Transactions on Computers Special Section on Emerging Non-Volatile Memory Technologies: From Devices to Architectures and Systems.

, , , and . IEEE Trans. Computers, 68 (8): 1111-1113 (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

An area and energy efficient design of domain-wall memory-based deep convolutional neural networks using stochastic computing., , , , , , , and . ISQED, page 314-321. IEEE, (2018)Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation., , , , , and . DAC, page 350-355. ACM, (2010)Compiler directed automatic stack trimming for efficient non-volatile processors., , , , , and . DAC, page 183:1-183:6. ACM, (2015)Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors., , , , and . ACM Trans. Embed. Comput. Syst., 13 (4): 79:1-79:25 (2014)Stack-Size Sensitive On-Chip Memory Backup for Self-Powered Nonvolatile Processors., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (11): 1804-1816 (2017)Data Placement and Duplication for Embedded Multicore Systems With Scratch Pad Memory., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (6): 809-817 (2013)Optimal scheduling to minimize non-volatile memory access time with hardware cache., , , , and . VLSI-SoC, page 131-136. IEEE, (2010)Algorithms for Optimally Arranging Multicore Memory Structures., , , , and . EURASIP J. Embed. Syst., (2010)Guest Editorial: IEEE Transactions on Computers Special Section on Emerging Non-Volatile Memory Technologies: From Devices to Architectures and Systems., , , and . IEEE Trans. Computers, 68 (8): 1111-1113 (2019)Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators., , , , , , and . IEEE Trans. Computers, 70 (4): 595-605 (2021)