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The evolution of IBM CMOS DRAM technology.

E. Adler, J. DeBrosse, S. Geissler, S. Holmes, M. Jaffe, J. Johnson, C. III, J. Lasky, B. Lloyd, G. Miles, J. Nakos, W. Jr., S. Voldman, M. Armacost, and R. Ferguson. IBM J. Res. Dev., 39 (1-2): 167-188 (1995)

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Aman K K Bhasin

K Böhm

K Schweizerhof

K Schaber

K Beheng

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Flexible test mode approach for 256-Mb DRAM.T. Kirihata, H. Wong, J. DeBrosse, Y. Watanabe, T. Hara, M. Yoshida, M. Wordeman, S. Fujii, Y. Asao, and B. Krsnik. IEEE J. Solid State Circuits, 32 (10): 1525-1534 (1997)Fault-tolerant designs for 256 Mb DRAM.T. Kirihata, Y. Watanabe, H. Wong, J. DeBrosse, M. Yoshida, D. Kato, S. Fujii, M. Wordeman, P. Poechmueller, S. Parke and 1 other author(s). IEEE J. Solid State Circuits, 31 (4): 558-566 (1996)Challenges and future directions for the scaling of dynamic random-access memory (DRAM).J. Mandelman, R. Dennard, G. Bronner, J. DeBrosse, R. Divakaruni, Y. Li, and C. Raden. IBM J. Res. Dev., 46 (2-3): 187-222 (2002)The evolution of IBM CMOS DRAM technology.E. Adler, J. DeBrosse, S. Geissler, S. Holmes, M. Jaffe, J. Johnson, C. III, J. Lasky, B. Lloyd, G. Miles and 5 other author(s). IBM J. Res. Dev., 39 (1-2): 167-188 (1995)A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs.H. Hoenigschmid, A. Frey, J. DeBrosse, T. Kirihata, G. Mueller, D. Storaska, G. Daniel, G. Frankowsky, K. Guay, D. Hanson and 11 other author(s). IEEE J. Solid State Circuits, 35 (5): 713-718 (2000)A 16-Mb MRAM featuring bootstrapped write drivers.D. Gogl, C. Arndt, J. Barwin, A. Bette, J. DeBrosse, E. Gow, H. Hoenigschmid, S. Lammers, M. Lamorey, Y. Lu and 10 other author(s). IEEE J. Solid State Circuits, 40 (4): 902-908 (2005)A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture.T. Kirihata, M. Gall, K. Hosokawa, J. Dortu, H. Wong, P. Pfefferl, B. Ji, O. Weinfurtner, J. DeBrosse, H. Terletzki and 4 other author(s). IEEE J. Solid State Circuits, 33 (11): 1711-1719 (1998)Design considerations for MRAM.T. Maffitt, J. DeBrosse, J. Gabric, E. Gow, M. Lamorey, J. Parenteau, D. Willmott, M. Wood, and W. Gallagher. IBM J. Res. Dev., 50 (1): 25-40 (2006)A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing.J. DeBrosse, T. Maffitt, Y. Nakamura, G. Jan, and P. Wang. CICC, page 1-3. IEEE, (2015)A high-speed 128-kb MRAM core for future universal memory applications.J. DeBrosse, D. Gogl, A. Bette, H. Hoenigschmid, R. Robertazzi, C. Arndt, D. Braun, D. Casarotto, R. Havreluk, S. Lammers and 5 other author(s). IEEE J. Solid State Circuits, 39 (4): 678-683 (2004)

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Disambiguation of "DeBrosse, John K."

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The evolution of IBM CMOS DRAM technology.

Please choose a person to relate this publication to

Aman K K Bhasin

K Böhm

K Schweizerhof

K Schaber

K Beheng

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "DeBrosse, John K."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML The evolution of IBM CMOS DRAM technology.

Please choose a person to relate this publication to

Aman K K Bhasin

K Böhm

K Schweizerhof

K Schaber

K Beheng

Other publications of authors with the same name

Disambiguation

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The evolution of IBM CMOS DRAM technology.