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Disambiguation of "Fiorenza, Giovanni"

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Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution.

, , , , and . ACM Great Lakes Symposium on VLSI, page 38-43. ACM, (2005)

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Francis Fiorenza

Luca Fiorenza

Fiorenza Deon

Fiorenza Falcioni

Fiorenza Rancan

 

Other publications of authors with the same name

Assessment of on-chip wire-length distribution models., , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (10): 1108-1112 (2004)Impact of interconnect length changes on effective materials properties (dielectric constant)., , and . SLIP, page 73-80. ACM, (2007)New simulation methodology for effects of radiation in semiconductor chip structures., , , , , and . IBM J. Res. Dev., 52 (3): 245-254 (2008)Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution., , , , and . ACM Great Lakes Symposium on VLSI, page 38-43. ACM, (2005)Estimating the efficiency of collaborative problem-solving, with applications to chip design., , , , , and . IBM J. Res. Dev., 47 (1): 77-88 (2003)Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models., , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (12): 1330-1347 (2004)The physical design of on-chip interconnections., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (3): 254-276 (2003)Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements., , and . IBM J. Res. Dev., 49 (4-5): 777-803 (2005)Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry., , and . SLIP, page 43-50. ACM, (2005)