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A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier.

, and . ReConFig, page 59-64. IEEE Computer Society, (2009)

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Power Aware Dividers in FPGA., , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 574-584. Springer, (2004)A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier., and . ReConFig, page 59-64. IEEE Computer Society, (2009)Accurate and flexible flow-based monitoring for high-speed networks., , , and . FPL, page 1-4. IEEE, (2013)Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks., , , , , and . IEEE Commun. Mag., 54 (3): 80-87 (2016)Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture., , , , , and . J. Syst. Archit., 58 (6-7): 247-256 (2012)Low-Power FSMs in FPGA: Encoding Alternatives., , , and . PATMOS, volume 2451 of Lecture Notes in Computer Science, page 363-370. Springer, (2002)FPGA Implementations of BCD Multipliers., , , , and . ReConFig, page 36-41. IEEE Computer Society, (2009)FPGA-based encrypted network traffic identification at 100 Gbit/s., , , and . ReConFig, page 1-6. IEEE, (2016)Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring applications., , , and . ReConFig, page 1-6. IEEE, (2016)Harnessing Programmable SoCs to develop cost-effective network quality monitoring devices., , , , , and . FPL, page 1-4. IEEE, (2016)