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A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS.

X. Sun, A. Boora, W. Zhang, V. Pamula, and V. Sathe. ISSCC, page 230-232. IEEE, (2019)

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A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS.X. Sun, A. Boora, W. Zhang, V. Pamula, and V. Sathe. ISSCC, page 230-232. IEEE, (2019)Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS.X. Sun, A. Boora, R. Pamula, C. Huang, D. Peña-Colaiocco, and V. Sathe. VLSI Circuits, page 1-2. IEEE, (2020)UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS.X. Sun, A. Boora, R. Pamula, C. Huang, D. Peña-Colaiocco, and V. Sathe. VLSI Circuits, page 1-2. IEEE, (2020)Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS.F. ur Rahman, R. Pamula, A. Boora, X. Sun, and V. Sathe. ISSCC, page 312-314. IEEE, (2019)

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Disambiguation of "Boora, Akshat"

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A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS.

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A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS.