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Resolving the memory bottleneck for single supply near-threshold computing.

, , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)

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Implementation of scalable power and area efficient high-throughput Viterbi decoders., , and . IEEE J. Solid State Circuits, 37 (7): 941-948 (2002)A framework for analyzing the propagation of hardware-induced errors in non-recursive LTI blocks with finite wordlength effects., , and . PATMOS, page 147-154. IEEE, (2016)A parametrizable low-power high-throughput turbo-decoder., , and . ICASSP (5), page 25-28. IEEE, (2005)FPGA-based Acceleration of Lidar Point Cloud Processing and Detection on the Edge., , , , , , and . IV, page 1-8. IEEE, (2023)Optimization of device dimensions for high-performance low-power architecture blocks., , , and . ESSCIRC, page 305-308. IEEE, (2003)Evaluating a New RRAM Manufacturing Test Strategy., , , and . LATS, page 1-6. IEEE, (2023)PHIDIAS: ultra-low-power holistic design for smart bio-signals computing platforms., , , , , , , , , and 2 other author(s). Conf. Computing Frontiers, page 309-314. ACM, (2016)Low-Cost DNN Hardware Accelerator for Wearable, High-Quality Cardiac Arrythmia Detection., , and . ASAP, page 213-216. IEEE, (2020)Lossless Sparse Temporal Coding for SNN-based Classification of Time-Continuous Signals., and . DATE, page 1-6. IEEE, (2023)Deadlock-Freedom in Computational Neuroscience Simulators., , , and . IEEE Des. Test, 39 (6): 70-78 (2022)