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Disambiguation of "Nakagome, Yoshinobu"

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Guest Editorial.

, and . IEEE J. Solid State Circuits, 38 (5): 687 (2003)

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Yoshinobu Kumazawa

 

Other publications of authors with the same name

Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs., , , , , and . IEEE J. Solid State Circuits, 29 (4): 448-453 (April 1994)Low-noise, high-speed data transmission using a ringing-canceling output buffer., , , , , and . IEEE J. Solid State Circuits, 30 (12): 1569-1574 (December 1995)A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits., , , , , and . IEEE J. Solid State Circuits, 30 (4): 487-490 (April 1995)A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM., , , and . IEEE J. Solid State Circuits, 34 (5): 653-660 (1999)An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 30 (11): 1165-1173 (November 1995)Introduction to the Special Issue., and . IEEE J. Solid State Circuits, 39 (4): 547-548 (2004)Guest Editorial., and . IEEE J. Solid State Circuits, 38 (5): 687 (2003)A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip., , , , , , , , and . IEEE J. Solid State Circuits, 32 (5): 635-641 (1997)Limitations and challenges of multigigabit DRAM chip design., , , and . IEEE J. Solid State Circuits, 32 (5): 624-634 (1997)A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer., , , , , , and . IEEE J. Solid State Circuits, 30 (3): 251-257 (March 1995)