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Two-phase resonant clocking for ultra-low-power hearing aid applications.

, , , , and . DATE, page 73-78. European Design and Automation Association, Leuven, Belgium, (2006)

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Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications., , , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 446-455. Springer, (2005)A Novel Thermomechanics -Based Lifetime Prediction Model for Cycle Fatigue Failure Mechanisms in Power Semiconductors., , , and . Microelectron. Reliab., 42 (9-11): 1653-1658 (2002)A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication., , , , , , , and . CICC, page 451-454. IEEE, (2007)42% power savings through glitch-reducing clocking strategy in a hearing aid application., , , , and . ISCAS, IEEE, (2006)A 0.67-mm2 45-μW DSP VLSI implementation of an adaptive directional microphone for hearing aids., , , , , , , , and . ECCTD, page 141-144. IEEE, (2005)FPGA implementation of a 2G fibre channel link encryptor with authenticated encryption mode GCM., , , and . SoC, page 1-4. IEEE, (2008)Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm., , , , , , , , and . DAC, page 558-561. ACM, (2006)Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (7): 830-836 (2008)Two-phase resonant clocking for ultra-low-power hearing aid applications., , , , and . DATE, page 73-78. European Design and Automation Association, Leuven, Belgium, (2006)