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Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding., , and . Inf. Process. Manag., 30 (6): 805-816 (1994)Accelerating Apache Spark with FPGAs., and . Concurr. Comput. Pract. Exp., (2019)The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning., , , and . Int. J. Parallel Program., 27 (5): 327-356 (1999)FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction., , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (2): 259-272 (2021)Disaggregated Memory in the Datacenter: A Survey., and . IEEE Access, (2023)Optimization of data prefetch helper threads with path-expression based statistical modeling., and . ICS, page 210-221. ACM, (2007)A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center., , , and . FPGA, page 262-271. ACM, (2019)NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstract., , and . FPL, page 1. IEEE, (2013)RACER: a reconfigurable constraint-length 14 Viterbi decoder., , and . FCCM, page 60-69. IEEE, (1996)An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDIC., , and . FPT, page 123-130. IEEE, (2014)