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Automating Hazard Checking in Transaction-Level Microarchitecture Models.

, and . FMCAD, page 62-65. IEEE Computer Society, (2007)

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Supporting RTL flow compatibility in a microarchitecture-level design framework., , , and . CODES+ISSS, page 343-352. ACM, (2009)Zchaff2004: An Efficient SAT Solver., , and . SAT (Selected Papers, volume 3542 of Lecture Notes in Computer Science, page 360-375. Springer, (2004)Utility of transaction-level hardware models in refinement checking., and . HLDVT, page 121-128. IEEE Computer Society, (2010)Verification Driven Formal Architecture and Microarchitecture Modeling., , , , and . MEMOCODE, page 123-132. IEEE Computer Society, (2007)Automating Hazard Checking in Transaction-Level Microarchitecture Models., and . FMCAD, page 62-65. IEEE Computer Society, (2007)Specification and encoding of transaction interaction properties., , and . Formal Methods Syst. Des., 39 (2): 144-164 (2011)Verification Languages., , and . Embedded Systems Handbook, CRC Press, (2005)