Author of the publication

mm2 inductive-coupling side-by-side chip link.

S. Hasegawa, J. Kadomoto, A. Kosuge, and T. Kuroda. ESSCIRC, page 469-472. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Daniel Junichiro Ruzicka

Other publications of authors with the same name

An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor.S. Mashimo, K. Inoue, R. Shioya, A. Fujita, R. Matsuo, S. Akaki, A. Fukuda, T. Koizumi, J. Kadomoto, H. Irie and 1 other author(s). FPT, page 63-71. IEEE, (2019)An inductive-coupling link for 3-D Network-on-Chips.J. Kadomoto, H. Amano, and T. Kuroda. ISOCC, page 150-151. IEEE, (2017)A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface.A. Nomura, J. Kadomoto, T. Kuroda, and H. Amano. CANDAR, page 126-131. IEEE Computer Society, (2017)Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface.A. Nomura, H. Matsutani, T. Kuroda, J. Kadomoto, Y. Matsushita, and H. Amano. CANDAR, page 195-201. IEEE Computer Society, (2016)Multi-Tree Network Protocol Enabling System Partitioning for Shape-Changeable Computer System.S. Nagasaki, J. Kadomoto, H. Irie, and S. Sakai. CF, ACM, (2024)Evaluation of Different Microarchitectures for Energy-Efficient RISC-V Cores.J. Kadomoto, H. Irie, and S. Sakai. MCSoC, page 78-84. IEEE, (2022)Analytical thruchip inductive coupling channel design optimization.L. Hsu, J. Kadomoto, S. Hasegawa, A. Kosuge, Y. Take, and T. Kuroda. ASP-DAC, page 731-736. IEEE, (2016)Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface.A. Nomura, Y. Matsushita, J. Kadomoto, H. Matsutani, T. Kuroda, and H. Amano. Int. J. Netw. Comput., 8 (1): 124-139 (2018)A High-Performance Out-of-Order Soft Processor Without Register Renaming.S. Mitsuno, J. Kadomoto, T. Koizumi, R. Shioya, H. Irie, and S. Sakai. FPL, page 73-78. IEEE, (2020)Accurate and Fast Performance Modeling of Processors with Decoupled Front-end.Y. Degawa, T. Koizumi, T. Nakamura, R. Shioya, J. Kadomoto, H. Irie, and S. Sakai. ICCD, page 88-92. IEEE, (2021)

BibSonomy

Disambiguation of "Kadomoto, Junichiro"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 1 Tb/s/mm2 inductive-coupling side-by-side chip link.

Please choose a person to relate this publication to

Daniel Junichiro Ruzicka

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Kadomoto, Junichiro"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1 Tb/s/mm2 inductive-coupling side-by-side chip link.

Please choose a person to relate this publication to

Daniel Junichiro Ruzicka

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 1 Tb/s/mm2 inductive-coupling side-by-side chip link.