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Design space exploration for 3D architectures., , , and . JETC, 2 (2): 65-103 (2006)Load Execution Latency Reduction., , , , , and . International Conference on Supercomputing, page 29-36. ACM, (1998)3D Processing Technology and Its Impact on iA32 Microprocessors., , , and . ICCD, page 316-318. IEEE Computer Society, (2004)Non-Vital Loads., , , and . HPCA, page 165-174. IEEE Computer Society, (2002)Can Trace-Driven Simulators Accurately Predict Superscalar Performance?, , , and . ICCD, page 478-485. IEEE Computer Society, (1996)Processor Design in 3D Die-Stacking Technologies., , and . IEEE Micro, 27 (3): 31-48 (2007)Hierarchical Scheduling Windows., , , and . MICRO, page 27-36. ACM/IEEE Computer Society, (2002)An integrated functional performance simulator., , , , , and . IEEE Micro, 19 (3): 26-35 (1999)Unleashing Fury: A New Paradigm for 3-D Design and Test., , , , , and . IEEE Des. Test, 34 (1): 8-15 (2017)Die Stacking (3D) Microarchitecture., , , , , , , , , and 5 other author(s). MICRO, page 469-479. IEEE Computer Society, (2006)