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Disambiguation of "Ghoushchi, Mohammad Bagher Ghaznavi"

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A fully pipelined and parallel hardware architecture for real-time BRISK salient point extraction.

, , , and . J. Real-Time Image Processing, 16 (5): 1859-1879 (2019)

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Mohammad Bagher Moarref

Mohammad-Bagher Khansari

Mohammad Bagher Sedghi

Mohammad Bagher Ghorbani

Maryam Mohammad Bagher Khan Tabrizi

 

Other publications of authors with the same name

Low-complexity and differential power analysis (DPA)-resistant two-folded power-aware Rivest-Shamir-Adleman (RSA) security schema implementation for IoT-connected devices., , and . IET Comput. Digit. Tech., 12 (6): 279-288 (2018)A power-performance partitioning approach for low-power DA-based FIR filter design with emphasis on datapath and controller., and . Int. J. Circuit Theory Appl., 50 (2): 427-447 (2022)A power-performance tunable logic with adjustable threshold pseudo-dynamic building blocks and CMOS compatibility., , and . I. J. Circuit Theory and Applications, 46 (4): 796-811 (2018)CSAM: A clock skew-aware aging mitigation technique., , , , and . Microelectron. Reliab., 55 (1): 282-290 (2015)Attribute-based collaborative filtering using genetic algorithm and weighted C-means algorithm., , and . Int. J. Bus. Inf. Syst., 13 (3): 265-283 (2013)TSSL: improving SSL/TLS protocol by trust model., , and . Secur. Commun. Networks, 8 (9): 1659-1671 (2015)Personalized recommendation of learning material using sequential pattern mining and attribute based collaborative filtering., , and . Educ. Inf. Technol., 19 (4): 713-735 (2014)Hardware architecture for projective model calculation and false match refining using random sample consensus algorithm., , , and . J. Electronic Imaging, 25 (6): 63014 (2016)A new low-power and low-complexity all digital PLL (ADPLL) in 180nm and 32nm., , , , and . ICECS, page 305-310. IEEE, (2010)Low-voltage and high-speed stand-alone multiple-input complex gates for error correction coding applications., and . Int. J. Circuit Theory Appl., 49 (4): 921-937 (2021)