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Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells., , , and . DTIS, page 1-5. IEEE, (2018)Effect-cause intra-cell diagnosis at transistor level., , , , , , and . ISQED, page 460-467. IEEE, (2013)A calculation method to estimate single event upset cross section., , , , , and . Microelectron. Reliab., (2017)Characterization of a RISC-V System-on-Chip under Neutron Radiation., , , , , , and . DTIS, page 1-6. IEEE, (2021)A Low-Cost Fault-Tolerant RISC-V Processor for Space Systems., , , , and . DTIS, page 1-5. IEEE, (2020)An effective ATPG flow for Gate Delay Faults., , , , , and . DTIS, page 1-6. IEEE, (2015)A built-in scheme for testing and repairing voltage regulators of low-power srams., , , , , , and . VTS, page 1-6. IEEE Computer Society, (2013)An effective hybrid fault-tolerant architecture for pipelined cores., , , , and . ETS, page 1-6. IEEE, (2015)Neutron detection in atmospheric environment through static and dynamic SRAM-based test bench., , , , , and . LATW, page 1-6. IEEE, (2011)Delay Fault Diagnosis in Sequential Circuits., , , , , , and . Asian Test Symposium, page 355-360. IEEE Computer Society, (2009)