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Disambiguation of "Shanbhag, Naresh R."

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A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array.

, , , and . IEEE J. Solid State Circuits, 53 (2): 642-655 (2018)

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Naresh Yallapragada

Uma-Naresh Niranjan

Naresh Bikash Dasgupta

Naresh Reddy Thumati

Naresh Chandra Varshneya

 

Other publications of authors with the same name

Joint Equalization and Coding for On-Chip Bus Communication., , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (3): 314-318 (2008)High-speed architectures for Reed-Solomon decoders., and . IEEE Trans. Very Large Scale Integr. Syst., 9 (5): 641-655 (2001)A pipelined adaptive NEXT canceller., and . IEEE Trans. Signal Process., 46 (8): 2252-2258 (1998)An improved systolic architecture for 2-D digital filters.. IEEE Trans. Signal Process., 39 (5): 1195-1202 (1991)System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near-Vt Computing., , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (9): 726-730 (2014)A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training., , and . IEEE J. Solid State Circuits, 53 (11): 3163-3173 (2018)Area-efficient high-throughput MAP decoder architectures., , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (8): 921-933 (2005)Analytical estimation of signal transition activity from word-level statistics., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (7): 718-733 (1997)Signal Processing for High-Speed Links., , and . Handbook of Signal Processing Systems, Springer, (2013)A Study of BER-Optimal ADC-Based Receiver for Serial Links., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (5): 693-704 (2016)