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Fuzzy logic approach to VLSI placement.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 2 (4): 489-501 (1994)

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Multiple project wafers for medium-volume IC production., and . ISCAS (5), page 4725-4728. IEEE, (2005)Multi-layer constrained via minimization with conjugate conflict continuation graphs., and . ISCAS (4), page 525-528. IEEE, (2004)Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs., , and . ACM Great Lakes Symposium on VLSI, page 37-42. ACM, (2011)Comments on "Filling algorithms and analyses for layout density control".. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (10): 1209-1211 (2002)Fuzzy logic approach to VLSI placement., , and . IEEE Trans. Very Large Scale Integr. Syst., 2 (4): 489-501 (1994)Variable-sized object packing and its applications to instruction cache design.. Comput. Electr. Eng., 34 (5): 438-444 (2008)Overview of the 2016 CAD contest at ICCAD., , , and . ICCAD, page 38. ACM, (2016)Weight-Based Bus-Invert Coding for Low-Power Applications., and . ASP-DAC/VLSI Design, page 121-125. IEEE Computer Society, (2002)Context-aware Post Routing Redundant Via Insertion., , , , and . ISVLSI, page 37-42. IEEE Computer Society, (2009)Standard Cell Like Via-Configurable Logic Block for Structured ASICs., , , and . ISVLSI, page 381-386. IEEE Computer Society, (2008)