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Preventing scan-based side-channel attacks through key masking.

, , and . DFT, page 1-4. IEEE Computer Society, (2017)

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Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients., , and . VTS, page 64-69. IEEE Computer Society, (2011)REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture., and . IOLTS, page 109-114. IEEE, (2016)SEU Tolerant Robust Latch Design., , , and . VDAT, volume 7373 of Lecture Notes in Computer Science, page 223-232. Springer, (2012)Instruction-Based Self-Testing of Delay Faults in Pipelined Processors., , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (11): 1203-1215 (2006)Soft-error reliable architecture for future microprocessors., and . IET Comput. Digit. Tech., 13 (3): 233-242 (2019)Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design., , , and . J. Electron. Test., 34 (1): 53-65 (2018)Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing., , and . J. Electron. Test., 28 (4): 541-549 (2012)Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients., , and . J. Electron. Test., 28 (5): 757-771 (2012)A PAM-4 10S/12S line coding scheme with equi-probable levels., , , and . ISCAS, page 1-5. IEEE, (2018)Locality-based Graph Reordering for Processing Speed-Ups and Impact of Diameter., and . CoRR, (2021)