( en | de | ru )

 

Disambiguation of "Navabi, Zainalabedin"

Author of the publication

copydeleteadd this publication to your clipboard
Effective RT-level software-based self-testing of embedded processor cores.

, and . DDECS, page 209-212. IEEE, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Kambiz Navabi

Foroogh Navabi-Kermani

 

Other publications of authors with the same name

Self-Healing Many-Core Architecture: Analysis and Evaluation., and . VLSI Design, (2016)On-Chip Verification of NoCs Using Assertion Processors., , , , and . DSD, page 535-538. IEEE Computer Society, (2007)An off-line MDSI interconnect BIST incorporated in BS 1149.1., , , and . ETS, page 1-2. IEEE, (2014)SCOAP-based Directed Random Test Generation for Combinational Circuits., , , and . EWDTS, page 1-5. IEEE, (2019)An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements., , , , , , and . EWDTS, page 1-6. IEEE, (2019)Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models., , , and . CHDL, volume A-32 of IFIP Transactions, page 569-586. North-Holland, (1993)Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment., , and . Embedded Systems and Applications, page 139-143. CSREA Press, (2003)A Low Power BIST Architecture for FPGA Look-Up Table Testing., and . VLSI-SOC, page 394-397. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Digital design and implementation with field programmable devices.. Kluwer, (2005)HDLs evolve as they affect design methodology for a higher abstraction and a better integration.. DTIS, page 1. IEEE, (2015)