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Exploration of Synthesis Methods from Simulink Models to FPGA for Aerospace Applications.

, , , , , and . CF, page 243-249. ACM, (2023)

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HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms., , , , , , , , , and 1 other author(s). IEEE Micro, 30 (5): 88-97 (2010)Performance modeling of embedded applications with zero architectural knowledge., and . CODES+ISSS, page 277-286. ACM, (2010)Bambu: A modular framework for the high level synthesis of memory-intensive applications., and . FPL, page 1-4. IEEE, (2013)Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis., , and . IEEE Des. Test, 35 (5): 54-62 (2018)Symbolic optimization of interacting controllers based onredundancy identification and removal., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (7): 760-772 (2000)Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks., , , , , and . DFT, page 223-230. IEEE Computer Society, (1993)An Expert Solution to Functional Testability Analysis of VLSI Circuits., , , , , and . SEKE, page 263-265. Knowledge Systems Institute, (1993)Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques., , , , and . DAC, page 467-470. ACM Press, (1996)End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators., , , , , , , , , and 1 other author(s). IEEE Trans. Computers, 71 (12): 3074-3087 (2022)SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels., , , , , , , , , and 3 other author(s). ARCS Workshops, VDE-Verlag, (2011)