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A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features., , , , , , , , , and 29 other author(s). IEEE J. Solid State Circuits, 58 (4): 1051-1061 (2023)Detection of Particulate Matters with a Field-Portable Microscope Using Side-Illuminated Total Internal Reflection., , , , and . Sensors, 21 (8): 2745 (2021)A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme., , , , , , , , , and 16 other author(s). IEEE J. Solid State Circuits, 56 (1): 199-211 (2021)An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process., , , , , and . IEEE Access, (2021)Parallel Interference Cancellation Scheme Based on Sorting Method for a Multi-Carrier DS/CDMA System., , and . IEICE Trans. Commun., 89-B (6): 1781-1792 (2006)A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features., , , , , , , , , and 28 other author(s). VLSI Technology and Circuits, page 130-131. IEEE, (2022)Outage Probability Analysis for DS-CDMA Systems with Call Admission Control Scheme., , and . IEICE Trans. Commun., 89-B (8): 2226-2229 (2006)A Microchip for High-Throughput Axon Growth Drug Screening., , , , and . Micromachines, 7 (7): 114 (2016)Hints for Memory Optimization of Asylo-based SGX Enclave Applications., , , , and . ICTC, page 1685-1690. IEEE, (2020)Student Session: Comparative Analysis of Live VM Migration with SGX Enclave., , , and . RTCSA, page 1-2. IEEE, (2020)