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Disambiguation of "Narayanan, Vijaykrishnan"

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Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2299-2309 (2016)

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P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

 

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Robust Coreset Construction for Distributed Machine Learning., , , , , and . IEEE J. Sel. Areas Commun., 38 (10): 2400-2417 (2020)Leakage Energy Management in Cache Hierarchies., , , , , , and . IEEE PACT, page 131-140. IEEE Computer Society, (2002)Fine-to-Coarse Object Classification of Very Large Images., and . ICIP, page 3498-3502. IEEE, (2023)Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only)., , , , and . FPGA, page 265. ACM, (2005)Editorial., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (1): 1 (2015)Ferroelectric Transistor based Non-Volatile Flip-Flop., , , , , and . ISLPED, page 10-15. ACM, (2016)A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays., , , , , and . ASP-DAC, page 118-123. IEEE, (2015)GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility., , , , , , , , , and 2 other author(s). IEEE Trans. Emerg. Top. Comput., 12 (1): 84-96 (January 2024)Modeling steep slope devices: From circuits to architectures., , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Hardware and Software Techniques for Controlling DRAM Power Modes., , , , and . IEEE Trans. Computers, 50 (11): 1154-1173 (2001)