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Disambiguation of "Iakymchuk, Taras"

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Versatile Direct and Transpose Matrix Multiplication with Chained Operations: An Optimized Architecture Using Circulant Matrices.

, , , , and . IEEE Trans. Computers, 65 (11): 3470-3479 (2016)

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Roman Iakymchuk

Taras Ptashnyk

Taras Chagala

Taras Vynnyk

Richard Taras

 

Other publications of authors with the same name

Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems., , , , , , , , and . ISCAS, page 1. IEEE, (2017)Event-based encoding from digital magnetic compass and ultrasonic distance sensor for navigation in mobile systems., , , , , and . INDIN, page 640-645. IEEE, (2016)Temperature-based covert channel in FPGA systems., , and . ReCoSoC, page 1-7. IEEE, (2011)Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems., , , , , , , , and . ISCAS, page 1-4. IEEE, (2017)An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links., , , , , , and . ISCAS, page 1556-1559. IEEE, (2014)Implementation of a new adaptive algorithm using fuzzy cost function and robust to impulsive noise., , , and . ICECS, page 45-48. IEEE, (2012)Versatile Direct and Transpose Matrix Multiplication with Chained Operations: An Optimized Architecture Using Circulant Matrices., , , , and . IEEE Trans. Computers, 65 (11): 3470-3479 (2016)Novel Resistance Measurement Method: Analysis of Accuracy and Thermal Dependence with Applications in Fiber Materials., , and . Sensors, 16 (12): 2129 (2016)Fast spiking neural network architecture for low-cost FPGA devices., , , and . ReCoSoC, page 1-6. IEEE, (2012)Hardware-efficient matrix inversion algorithm for complex adaptive systems., , , and . ICECS, page 41-44. IEEE, (2012)