( en | de | ru )

 

Disambiguation of "Sarbazi-Azad, Hamid"

Author of the publication

copydeleteadd this publication to your clipboard
Application-Aware Topology Reconfiguration for On-Chip Networks.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (11): 2010-2022 (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ataollah Azadi-Bakhsh

Mohsen Azadbakht

Esfandyar Azadi-Rad

Hassan Azadeh

Behnam Azadegan

 

Other publications of authors with the same name

Advances in multicore systems architectures., , and . J. Supercomput., 71 (8): 2783-2786 (2015)NURA: A Framework for Supporting Non-Uniform Resource Accesses in GPUs., , , , , and . Proc. ACM Meas. Anal. Comput. Syst., 6 (1): 16:1-16:27 (2022)Detecting Threats in Star Graphs., , , and . IEEE Trans. Parallel Distributed Syst., 20 (4): 474-483 (2009)Preface., and . Adv. Comput., (2022)High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement., , and . ISLPED, page 79-84. IEEE/ACM, (2011)An efficient DVS scheme for on-chip networks using reconfigurable Virtual Channel allocators., , , and . ISLPED, page 249-254. IEEE, (2015)Chapter Six - Topology Specialization for Networks-on-Chip in the Dark Silicon Era., and . Advances in Computers, (2018)Chapter One - Dark Silicon and the History of Computing., and . Advances in Computers, (2018)Power- and performance-efficient cluster-based network-on-chip with reconfigurable topology., , and . Microprocess. Microsystems, (2016)Communication delay in hypercubes in the presence of bit-reversal traffic., , and . Parallel Comput., 27 (13): 1801-1816 (2001)