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Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design.

, , , , , and . DATE, page 352-357. IEEE Computer Society, (2004)

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Combining RC-Interconnect Effects with Nonlinear MOS Macromodels., and . ISCAS, page 570-573. IEEE, (1995)Design challenges for next-generation multimedia, game and entertainment platforms., , , , and . DAC, page 459. ACM, (2006)Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture., , , , , , , and . DATE, page 138-139. IEEE Computer Society, (2005)Performance Improvement for High Speed Devices Using E-tests and the SPICE Model., , , , , , , and . ISQED, page 443-447. IEEE Computer Society, (2001)Dynamic power estimation using the probabilistic contribution measure (PCM)., , , , , and . ISLPED, page 279-281. ACM, (1999)A systematic IP and bus subsystem modeling for platform-based system design., , , , , , , and . DATE, page 560-564. European Design and Automation Association, Leuven, Belgium, (2006)SoC in Nanoera: Challenges and Endless Possibility.. DATE, page 2. IEEE Computer Society, (2005)Runtime distribution-aware dynamic voltage scaling., , , , , and . ICCAD, page 587-594. ACM, (2006)SilcVerify: An Efficient Substrate Coupling Noise Simulation Tool for High-Speed & Nano-Scaled Memory Design., , , , and . ISQED, page 475-480. IEEE Computer Society, (2007)Sensing Margin Analysis of MLC Flash Memories Using a Novel Unified Statistical Model., , , , , , , and . ISQED, page 185-189. IEEE Computer Society, (2006)