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Synthesis of Application-Specific Fault-Tolerant Digital Microfluidic Biochip Architectures.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (5): 764-777 (2016)

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Recent research and emerging challenges in the System-Level Design of digital microfluidic biochips., , and . SoCC, page 6-11. IEEE, (2011)System-level modeling and synthesis of flow-based microfluidic biochips., , and . CASES, page 225-234. ACM, (2011)Routing-based synthesis of digital microfluidic biochips., , and . CASES, page 41-50. ACM, (2010)Application-aware optimization of redundant resources for the reconfigurable self-healing eDNA hardware architecture., , and . AHS, page 66-73. IEEE, (2011)Design optimisation of cyber-physical distributed systems using IEEE time-sensitive networks., , , and . IET Cyper-Phys. Syst.: Theory & Appl., 1 (1): 86-94 (2016)The FORA Fog Computing Platform for Industrial IoT., , , , , , and . CoRR, (2020)Configuration optimization for heterogeneous time-sensitive networks., , , , and . Real Time Syst., 59 (4): 705-747 (December 2023)System-level synthesis of multi-ASIP platforms using an uncertainty model., , and . Integr., (2015)Real-Time Traffic Guarantees in Heterogeneous Time-sensitive Networks., , , , and . RTNS, page 46-57. ACM, (2022)Special Session: Digital Technologies for Sustainability - Research Challenges and Opportunities., , , and . CODES+ISSS, page 18-23. IEEE, (2023)