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Reducing branch misprediction penalties via dynamic control independence detection.

, , and . International Conference on Supercomputing, page 109-118. ACM, (1999)

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An in-depth analysis of the impact of processor affinity on network performance., , and . ICON, page 244-250. IEEE, (2004)Architectural Characterization of Processor Affinity in Network Processing., , , , , and . ISPASS, page 207-218. IEEE Computer Society, (2005)Reducing branch misprediction penalties via dynamic control independence detection., , and . International Conference on Supercomputing, page 109-118. ACM, (1999)Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL., , , , , , , , and . ICCAD, page 1-9. IEEE, (2023)An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors., , , , , , , , and . IEEE Trans. Computers, 72 (1): 222-235 (2023)Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS., , , , , and . VLSID, page 443-448. IEEE, (2024)Formal Verification of Security Critical Hardware-Firmware Interactions in Commercial SoCs., , , , and . DAC, page 43. ACM, (2019)Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware., , , , and . DAC, page 91:1-91:6. ACM, (2018)Hardware-Supported Patching of Security Bugs in Hardware IP Blocks., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (1): 54-67 (2023)Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (2): 228-251 (2021)