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Improving the Performance of Block-based DRAM Caches Via Tag-Data Decoupling., , and . IEEE Trans. Computers, 70 (11): 1914-1927 (2021)ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees., , , , , and . IEEE Trans. Computers, 72 (5): 1488-1502 (May 2023)DNA Pre-alignment Filter using Processing Near Racetrack Memory., , , , and . CoRR, (2022)BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack Memory., , , , , and . DAC, page 1111-1116. IEEE, (2021)SHRIMP: Efficient Instruction Delivery with Domain Wall Memory., , , , and . ISLPED, page 1-6. IEEE, (2019)BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (12): 5288-5298 (2022)Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade., , , , , , and . Proc. IEEE, 108 (8): 1303-1321 (2020)A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement., and . IEEE Trans. Very Large Scale Integr. Syst., 27 (10): 2375-2386 (2019)ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0., , , , and . CoRR, (2019)Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories., , , and . ACM Trans. Embed. Comput. Syst., 19 (6): 44:1-44:26 (2020)