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Hierarchy-aware and area-efficient test infrastructure design for core-based system chips.

, , , и . DATE, стр. 285-290. European Design and Automation Association, Leuven, Belgium, (2006)

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Test access mechanism for multiple identical cores., , , , и . ITC, стр. 1-10. IEEE Computer Society, (2009)Yield analysis for repairable embedded memories., , , , , и . ETW, стр. 35-40. IEEE Computer Society, (2003)Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs., и . ICCAD, стр. 88-93. IEEE Computer Society, (2005)IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores., , , и . ITC, стр. 1203-1212. IEEE Computer Society, (2004)Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores., , , и . DATE, стр. 50-55. IEEE Computer Society, (2005)Test cost reduction for the AMD™ Athlon processor using test partitioning., , и . ITC, стр. 1-10. IEEE Computer Society, (2007)Test Access Mechanism for Multiple Identical Cores., , , , и . ITC, стр. 1-10. IEEE Computer Society, (2008)A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs., , и . ICCD, стр. 137-142. IEEE Computer Society, (2005)Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures., и . DATE, стр. 422-427. IEEE Computer Society, (2004)Hierarchy-aware and area-efficient test infrastructure design for core-based system chips., , , и . DATE, стр. 285-290. European Design and Automation Association, Leuven, Belgium, (2006)