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Disambiguation of "Takizawa, Hiroyuki"

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An energy-efficient dynamic memory address mapping mechanism.

, , , , , and . COOL Chips, page 1-3. IEEE Computer Society, (2015)

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Hiroyuki Tan

Hiroyuki Kobayashi

Chieko Takizawa

Hiroyuki Okamuro

Hiroyuki Takada

 

Other publications of authors with the same name

Hierarchical parallel processing of large scale data clustering on a PC cluster with GPU co-processing., and . J. Supercomput., 36 (3): 219-234 (2006)A Machine Learning-Based Approach for Selecting SpMV Kernels and Matrix Storage Formats., , , and . IEICE Trans. Inf. Syst., 101-D (9): 2307-2314 (2018)Online MPI Process Mapping for Coordinating Locality and Memory Congestion on NUMA Systems., , , and . Supercomput. Front. Innov., 7 (1): 71-90 (2020)A power-aware shared cache mechanism based on locality assessment of memory reference for CMPs., , , and . MEDEA@PACT, page 113-120. ACM, (2007)Modeling of cache access behavior based on Zipf's law., , , and . MEDEA@PACT, page 9-15. ACM, (2008)A Real-time Flood Inundation Prediction on SX-Aurora TSUBASA., , , , , , , and . HIPC, page 192-197. IEEE, (2022)Spatiotemporal Anomaly Detection for Large-Scale Sensor Data., , and . PAAP, page 162-168. IEEE, (2021)Improving the Accuracy in SpMV Implementation Selection with Machine Learning., , , , and . CANDAR (Workshops), page 172-177. IEEE, (2020)A memory bank conflict prevention mechanism for SYCL on SX-Aurora TSUBASA., , , and . CANDAR (Workshops), page 217-222. IEEE, (2021)Evaluating I/O Acceleration Mechanisms of SX-Aurora TSUBASA., , , and . IPDPS Workshops, page 752-759. IEEE, (2021)