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Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs., , , , , , , and . IEEE Access, (2021)In-Depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications Using One-and- Two -Step Design Optimization., , , , and . IEEE Access, (2021)Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology., , , , , , , , and . Integr., (2018)Automatic Design of High-Gain 26.5-to-29.5-GHz Transformer-Less Low-Noise Amplifier 1.86-to-8.87-mW Variants in 65-nm CMOS., , , , and . ISCAS, page 1988-1992. IEEE, (2022)New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization., , , , , , , , and . SMACD, page 1-4. IEEE, (2017)Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models., , , , , , , , , and 2 other author(s). SMACD, page 73-76. IEEE, (2018)Frequency-dependent parameterized macromodeling of integrated inductors., , , , , , and . SMACD, page 1-4. IEEE, (2016)Analythical characterization of variable width integrated spiral inductors., , and . MIXDES, page 586-591. IEEE, (2013)Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing., , , , , , , and . SMACD, page 13-16. IEEE, (2019)Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling., , , , , , and . SMACD, page 1-4. IEEE, (2022)