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Disambiguation of "Agarwal, Sapan"

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Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator.

, , , , , , , , and . CoRR, (2017)

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Sapan Bhatia

Suman Agarwal

Swarna Agarwal

Seema Agarwal

Jugalkishor Agarwal

 

Other publications of authors with the same name

Impact of Linearity and Write Noise of Analog Resistive Memory Devices in a Neural Algorithm Accelerator., , , , , , , , and . ICRC, page 1-10. IEEE, (2017)Resistive memory device requirements for a neural algorithm accelerator., , , , , , , and . IJCNN, page 929-938. IEEE, (2016)Analog Neural Network Inference Accuracy in One-Selector One-Resistor Memory Arrays., , , , , , , , and . ICRC, page 7-12. IEEE, (2022)TCAM-SSD: A Framework for Search-Based Computing in Solid-State Drives., , , , , , and . CoRR, (2024)On the Accuracy of Analog Neural Network Inference Accelerators., , , , , , , and . CoRR, (2021)TID Response of an Analog In-Memory Neural Network Accelerator., , , , , , , , , and 1 other author(s). IRPS, page 1-6. IEEE, (2023)Device-aware inference operations in SONOS nonvolatile memory arrays., , , , , , , , , and 3 other author(s). IRPS, page 1-6. IEEE, (2020)Biological Dynamics Enabling Training of Binary Recurrent Networks., , , , , and . NICE, page 1-7. IEEE, (2024)An Analog Preconditioner for Solving Linear Systems., , , , , , , , and . HPCA, page 761-774. IEEE, (2021)ATHENA: Enabling Codesign for Next-Generation AI/ML Architectures., , , , , , , and . ICRC, page 13-23. IEEE, (2022)