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Disambiguation of "Ünsal, Osman S."

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Power and Accuracy of Multi-Layer Perceptrons (MLPs) under Reduced-voltage FPGA BRAMs Operation.

, , and . CoRR, (2020)

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Merâl Ünsal

Ünsal Pul

Tülin Ünsal

Feyzan Ünsal

Ayhan Ünsalan

 

Other publications of authors with the same name

Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core., , , , and . IEEE Comput. Archit. Lett., 14 (2): 160-163 (2015)Memory Controller for Vector Processor., , , , and . J. Signal Process. Syst., 90 (11): 1533-1549 (2018)Power and Accuracy of Multi-Layer Perceptrons (MLPs) under Reduced-voltage FPGA BRAMs Operation., , and . CoRR, (2020)Chapter One - An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques., , , , and . Advances in Computers, (2015)Rapid Development of Error-Free Architectural Simulators Using Dynamic Runtime Testing., , , and . SBAC-PAD, page 80-87. IEEE Computer Society, (2011)Exploiting Inactive Rename Slots for Detecting Soft Errors., , , and . ARCS, volume 5974 of Lecture Notes in Computer Science, page 126-137. Springer, (2010)Stand-Alone Memory Controller for Graphics System., , , , , , and . ARC, volume 8405 of Lecture Notes in Computer Science, page 108-120. Springer, (2014)Efficient thread-to-core mapping alternatives for application-level redundant multithreading., and . Concurr. Comput. Pract. Exp., (2023)A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs., , and . FPL, page 451-452. IEEE Computer Society, (2018)CRC-Based Memory Reliability for Task-Parallel HPC Applications., , , , and . IPDPS, page 1101-1112. IEEE Computer Society, (2016)