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Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent?

, , , , , and . DATE, page 668-669. IEEE Computer Society, (2004)

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Partial Precedence Constrained Scheduling.. IEEE Trans. Computers, 48 (10): 1127-1130 (1999)Admissibility of A0* when Heuristics Overestimate., , and . Artif. Intell., 34 (1): 97-113 (1987)A verification system for transient response of analog circuits., and . ACM Trans. Design Autom. Electr. Syst., 12 (3): 31:1-31:39 (2007)Simulation-based verification using Temporally Attributed Boolean Logic., , , and . ACM Trans. Design Autom. Electr. Syst., 13 (4): 63:1-63:52 (2008)Register-interconnect optimization in data path synthesis., , and . Microprocess. Microprogramming, 33 (5): 279-288 (1992)Robust embedded software design through early analysis of quality faults., , and . ISEC, page 31-40. ACM, (2011)Complexity of Compositional Model Checking of Computation Tree Logic on Simple Structures., , and . IWDC, volume 3326 of Lecture Notes in Computer Science, page 102-113. Springer, (2004)Distributed Evolutionary Algorithm Search for Multiobjective Spanning Tree Problem., , and . IWDC, volume 3326 of Lecture Notes in Computer Science, page 538. Springer, (2004)Open Computation Tree Logic for Formal Verification of Modules., , and . ASP-DAC/VLSI Design, page 735-740. IEEE Computer Society, (2002)Execution Ordering in AND/OR Graphs with Failure Probabilities., , and . SOCS, page 41-48. AAAI Press, (2012)