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Disambiguation of "Hong, Xianlong"

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A novel thermal optimization flow using incremental floorplanning for 3D ICs.

, , and . ASP-DAC, page 347-352. IEEE, (2009)

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Moon-Shin Hong

Jung-soo Hong

Youn-Ho Hong

Hong Guo

Seong-Bang Hong

 

Other publications of authors with the same name

Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain., , , and . J. Comput. Sci. Technol., 20 (2): 224-230 (2005)Leakage power optimization for clock network using dual-Vth technology., , and . ISCAS, page 2769-2772. IEEE, (2008)Interconnect delay optimization via high level re-synthesis after floorplanning., , and . ISCAS (6), page 5641-5644. IEEE, (2005)Timing-driven global routing with efficient buffer insertion., , and . ISCAS (3), page 2449-2452. IEEE, (2005)VLSI block placement with alignment constraints based on corner block list., , , , and . ISCAS (6), page 6222-6225. IEEE, (2005)Evaluating a bounded slice-line grid assignment in O(nlogn) time., , , , , , and . ISCAS (4), page 708-711. IEEE, (2003)Buffer planning based on block exchanging., , , and . ISCAS, IEEE, (2006)Performance-Driven Steiner Tree Algorithm for Global Routing., , , , and . DAC, page 177-181. ACM Press, (1993)A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design., , , , and . SAMOS, volume 3553 of Lecture Notes in Computer Science, page 344-353. Springer, (2005)VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (12): 3136-3147 (2003)