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Disambiguation of "Mahapatra, Nihar R."

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Partitioned reuse cache for energy-efficient soft-error protection of functional units.

, and . SoCC, page 17-20. IEEE, (2008)

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Lakshman Mahapatra

Suddhasatta Mahapatra

Nihar Jangle

Subhashree Mahapatra

Nihar Ranjan Kundu

 

Other publications of authors with the same name

A Comparative Assessment of Predictive Accuracies of Conventional and Machine Learning Scoring Functions for Protein-Ligand Binding Affinity Prediction., and . IEEE ACM Trans. Comput. Biol. Bioinform., 12 (2): 335-347 (2015)Scalable Global and Local Hashing Strategies for Duplicate Pruning in Parallel A* Graph Search., and . IEEE Trans. Parallel Distributed Syst., 8 (7): 738-756 (1997)An efficient error-masking technique for improving the soft-error robustness of static CMOS circuits., and . SoCC, page 227-230. IEEE, (2004)Node-Covering, Error-Correcting Codes and Multiprocessors with Very High Average Fault Tolerance., and . IEEE Trans. Computers, 46 (9): 997-1015 (1997)Partitioned reuse cache for energy-efficient soft-error protection of functional units., and . SoCC, page 17-20. IEEE, (2008)Ethical Considerations in AI-Based Recruitment., and . ISTAS, page 1-7. IEEE, (2019)Adaptive Quality Equalizing: High-performance load balancing for parallel branch-and-bound across applications and computing systems., and . Parallel Comput., 30 (5-6): 867-881 (2004)A Comparative Assessment of Conventional and Machine-Learning-Based Scoring Functions in Predicting Binding Affinities of Protein-Ligand Complexes., and . BIBM, page 627-630. IEEE Computer Society, (2011)Increasing the energy efficiency of pipelined circuits via slack redistribution., and . ACM Great Lakes Symposium on VLSI, page 436-441. ACM, (2005)Efficient techniques based on gate triggering for designing static CMOS ICs with very low glitch power dissipation., , and . ISCAS, page 537-540. IEEE, (2000)