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Optimal Scheduling and Allocation for IC Design Management and Cost Reduction.

P. Agrawal, M. Broxterman, B. Chatterjee, P. Cuevas, K. Hayashi, A. Kahng, P. Myana, and S. Nath. ACM Trans. Design Autom. Electr. Syst., 22 (4): 60:1-60:30 (2017)

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Siddhartha Chattopadhyay

Siddhartha Roy

Siddhartha Kargupta

Siddhartha Schwenzer

Siddhartha Chib

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BufFormer: A Generative ML Framework for Scalable Buffering.R. Liang, S. Nath, A. Rajaram, J. Hu, and H. Ren. ASP-DAC, page 264-270. ACM, (2023)Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process Nodes.S. Nath, and V. Khandelwal. ISPD, page 83-90. ACM, (2021)Generative self-supervised learning for gate sizing: invited.S. Nath, G. Pradipta, C. Hu, T. Yang, B. Khailany, and H. Ren. DAC, page 1331-1334. ACM, (2022)Toward Metrics of Design Automation Research Impact.A. Kahng, M. Luo, G. Nam, S. Nath, D. Pan, and G. Robins. ICCAD, page 263-270. IEEE, (2015)Methodology for electromigration signoff in the presence of adaptive voltage scaling.W. Chan, A. Kahng, and S. Nath. SLIP, page 6:1-6:7. IEEE Computer Society, (2014)Optimal Scheduling and Allocation for IC Design Management and Cost Reduction.P. Agrawal, M. Broxterman, B. Chatterjee, P. Cuevas, K. Hayashi, A. Kahng, P. Myana, and S. Nath. ACM Trans. Design Autom. Electr. Syst., 22 (4): 60:1-60:30 (2017)High-dimensional metamodeling for prediction of clock tree synthesis outcomes.A. Kahng, B. Lin, and S. Nath. SLIP, page 1-7. IEEE Computer Society, (2013)Learning-based prediction of embedded memory timing failures during initial floorplan design.W. Chan, K. Chung, A. Kahng, N. MacDonald, and S. Nath. ASP-DAC, page 178-185. IEEE, (2016)A deep learning methodology to proliferate golden signoff timing.S. Han, A. Kahng, S. Nath, and A. Vydyanathan. DATE, page 1-6. European Design and Automation Association, (2014)Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session Paper.H. Ren, S. Godil, B. Khailany, R. Kirby, H. Liao, S. Nath, J. Raiman, and R. Roy. ICCAD, page 1-6. IEEE, (2021)

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Disambiguation of "Nath, Siddhartha"

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Optimal Scheduling and Allocation for IC Design Management and Cost Reduction.

Please choose a person to relate this publication to

Siddhartha Chattopadhyay

Siddhartha Roy

Siddhartha Kargupta

Siddhartha Schwenzer

Siddhartha Chib

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Nath, Siddhartha"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Optimal Scheduling and Allocation for IC Design Management and Cost Reduction.

Please choose a person to relate this publication to

Siddhartha Chattopadhyay

Siddhartha Roy

Siddhartha Kargupta

Siddhartha Schwenzer

Siddhartha Chib

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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APA
Chicago
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Optimal Scheduling and Allocation for IC Design Management and Cost Reduction.