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Statistical Power Estimation for FPGA.

, , , и . FPL, стр. 515-518. IEEE, (2005)

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Другие публикации лиц с тем же именем

Power Aware Dividers in FPGA., , , и . PATMOS, том 3254 из Lecture Notes in Computer Science, стр. 574-584. Springer, (2004)A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation., , , , и . ICECS, стр. 241-244. IEEE, (1999)Statistical Power Estimation for FPGA., , , и . FPL, стр. 515-518. IEEE, (2005)Rapid prototyping of a self-timed ALU with FPGAs., , , и . ReConFig, IEEE Computer Society, (2005)FSM Decomposition for Low Power in FPGA., , , и . FPL, том 2438 из Lecture Notes in Computer Science, стр. 350-359. Springer, (2002)Design and FPGA implementation of digit-serial FIR filters., , , и . ICECS, стр. 191-194. IEEE, (1998)A-B Nodes Classification for Power Estimation., и . FPL, стр. 1-6. IEEE, (2006)A Framework to Compare Estimated and Measured Power Consumption on FPGAs., , и . J. Low Power Electron., 15 (4): 329-337 (2019)Fast FPGA-based pipelined digit-serial/parallel multipliers., , , и . ISCAS (1), стр. 482-485. IEEE, (1999)Some Notes on Power Management on FPGA-Based Systems., , , и . FPL, том 975 из Lecture Notes in Computer Science, стр. 149-157. Springer, (1995)