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Disambiguation of "Katelman, Michael"

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Getting Formal Verification into Design Flow.

, , and . FM, volume 5014 of Lecture Notes in Computer Science, page 12-32. Springer, (2008)

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Michael Bode

Le groupe international de sociétés: le système de conflit de lois en droit comparé français et allemand. HU Berlin, (2009)

Michael Liecke

Subnationale Clusterpolitik: die Biotechnologiepolitik deutscher Länder im Vergleich. Uni München, (2009)

Michael Schoierer

NS-Diktatur, Anomie und Demokratisierung Westdeutschlands. Uni Augsburg, (2007)

Michael Krug

X-ray crystallographic analysis of the archaeal transcriptional regulator TrmB and development of a graphical user interface for the monochromatic diffraction data processing software XDS. Uni Konstanz, (2009)

Michael Bernateck

Komplexes Regionales Schmerzsyndrom Typ 1 (M.Sudeck): neue Aspekte zur Symptomatologie, Pathogenese, Diagnostik und Therapie. MedH Hannover, habilitation, (2009)
 

Other publications of authors with the same name

Concurrent Rewriting Semantics and Analysis of Asynchronous Digital Circuits., , and . WRLA, volume 6381 of Lecture Notes in Computer Science, page 140-156. Springer, (2010)Redesign of the LMST Wireless Sensor Protocol through Formal Modeling and Statistical Model Checking., , and . FMOODS, volume 5051 of Lecture Notes in Computer Science, page 150-169. Springer, (2008)Rewriting semantics of production rule sets., , and . J. Log. Algebraic Methods Program., 81 (7-8): 929-956 (2012)vlogsl: A Strategy Language for Simulation-Based Verification of Hardware., and . Haifa Verification Conference, volume 6504 of Lecture Notes in Computer Science, page 129-145. Springer, (2010)Staging static analyses for program generation., , and . GPCE, page 1-10. ACM, (2006)A meta-language for functional verification. University of Illinois Urbana-Champaign, USA, (2011)A Rewriting Semantics for ABEL with Applications to Hardware/Software Co-Design and Analysis., and . WRLA, volume 176 of Electronic Notes in Theoretical Computer Science, page 47-60. Elsevier, (2006)Getting Formal Verification into Design Flow., , and . FM, volume 5014 of Lecture Notes in Computer Science, page 12-32. Springer, (2008)Using the PALS Architecture to Verify a Distributed Topology Control Protocol for Wireless Multi-Hop Networks in the Presence of Node Failures, and . RTRTS, volume 36 of EPTCS, page 101-116. (2010)A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits., , and . ASYNC, page 65-76. IEEE Computer Society, (2009)