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Co-simulation framework for streamlining microprocessor development on standard ASIC design flow., , , , and . ASP-DAC, page 400-405. IEEE, (2014)Non-uniform program analysis & repeatable execution constraints: exploiting out-of-order processors in real-time systems., and . SIGBED Review, 3 (1): 17-22 (2006)Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing., , , and . CASES, page 213-224. ACM, (2005)A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors., and . IEEE Trans. Computers, 53 (4): 399-413 (2004)Control Independence in Trace Processors., and . J. Instruction-Level Parallelism, (2000)Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching., , and . IEEE Trans. Computers, 64 (8): 2182-2203 (2015)Post-Silicon Microarchitecture., , , , , , and . IEEE Comput. Archit. Lett., 19 (1): 26-29 (2020)Adaptive Mode Control: A Static-Power-Efficient Cache Design., , , and . IEEE PACT, page 61-70. IEEE Computer Society, (2001)Control-Flow Decoupling., , and . MICRO, page 329-340. IEEE Computer Society, (2012)Assigning Confidence to Conditional Branch Predictions., , and . MICRO, page 142-152. ACM/IEEE Computer Society, (1996)