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Disambiguation of "Lo, Shih-Hsien"

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Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices.

, , , , , , and . Microelectron. J., 38 (8-9): 931-941 (2007)

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Shih-Hsien Kuo

Shih-Kung Lo

Yichang Shih

Linda Hsien

Shih-En Shih

 

Other publications of authors with the same name

Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits., , , , , , and . ISQED, page 410-415. IEEE Computer Society, (2005)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference., , , , , , , , , and 33 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header., , and . VLSI Design, page 758-761. IEEE Computer Society, (2006)Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices., , , , , , and . Microelectron. J., 38 (8-9): 931-941 (2007)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference., , , , , , , , , and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides., , and . IBM J. Res. Dev., 43 (3): 327-338 (1999)CMOS scaling into the nanometer regime., , , , , , , , , and 1 other author(s). Proc. IEEE, 85 (4): 486-504 (1997)Across the Stack Opportunities for Deep Learning Acceleration., , , , , , , , , and 21 other author(s). ISLPED, page 35:1-35:2. ACM, (2018)Efficient AI System Design With Cross-Layer Approximate Computing., , , , , , , , , and 30 other author(s). Proc. IEEE, 108 (12): 2232-2250 (2020)