( en | de | ru )

 

Disambiguation of "Noll, Tobias G."

Author of the publication

copydeleteadd this publication to your clipboard
Limits of gate-level power estimation considering real delay effects and glitches.

, and . ISSoC, page 1-7. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tobias Nöll

Tobias Noll

Tobias Noll

Tobias Gebhard Noll

Tobias G Wenzl

 

Other publications of authors with the same name

An accurate power estimation model for low-power hierarchical-architecture SRAMs., and . VLSI-SoC, page 144-149. IEEE, (2013)Noise Margin Based Library Optimization Considering Variability in Sub-threshold., , and . PATMOS, volume 7606 of Lecture Notes in Computer Science, page 72-82. Springer, (2012)A Physically Oriented Model to Quantify the Noise-on-Delay Effect., and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 879-888. Springer, (2004)A radix-4 single-precision floating point divider based on digit set interleaving., and . ISCAS, page 709-712. IEEE, (2010)Verbesserung der Dynamik und Ortsauflösung in der Ultraschalldiagnostik durch die Kombination kodierter Anregung und tiefenangepaßter Mismatched-Filterung., , , and . Bildverarbeitung für die Medizin, volume 12 of CEUR Workshop Proceedings, Springer, (1998)Artefaktreduzierung in der ultraschnellen Magnetresonanz-Bildgebung mittels inverser Filterung im Ortsfrequenzbereich., , and . Bildverarbeitung für die Medizin, volume 6 of CEUR Workshop Proceedings, CEUR-WS.org, (1996)A hybrid CMOS/memristive nanoelectronic circuit for programming synaptic weights., and . ESANN, (2012)Carry-save architectures for high-speed digital signal processing.. VLSI Signal Processing, 3 (1-2): 121-140 (1991)Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations., , , , , , , and . ACM Comput. Surv., 47 (3): 38:1-38:33 (2015)A new scalable VLSI architecture for Reed-Solomon decoders., , and . CICC, page 13-16. IEEE, (1998)