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Compact models and model standard for 2.5D and 3D integration.

, and . SLIP, page 7:1-7:7. IEEE Computer Society, (2014)

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Exploring memory controller configurations for many-core systems with 3D stacked DRAMs., , , and . ISQED, page 565-570. IEEE, (2015)Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression., and . SoCC, page 193-196. IEEE, (2006)Leakage Optimized DECAP Design for FPGAs., , , , and . APCCAS, page 960-963. IEEE, (2006)Reliability-aware Co-synthesis for Embedded Systems., , , , and . VLSI Signal Processing, 49 (1): 87-99 (2007)Augmenting Platform-Based Design with Synthesis Tools., , and . Journal of Circuits, Systems, and Computers, 12 (2): 125-142 (2003)Discriminative Reverse Sparse Tracking via Weighted Multitask Learning., , , , and . IEEE Trans. Circuits Syst. Video Techn., 27 (5): 1031-1042 (2017)RADAR: a 3D-reRAM based DNA alignment accelerator architecture., , , and . DAC, page 59:1-59:6. ACM, (2018)Power and performance of read-write aware Hybrid Caches with non-volatile memories., , , , and . DATE, page 737-742. IEEE, (2009)Image captioning via hierarchical attention mechanism and policy gradient optimization., , , , , and . Signal Process., (2020)E-Booster: A Field-Programmable Gate Array-Based Accelerator for Secure Tree Boosting Using Additively Homomorphic Encryption., , , , , , , , , and 4 other author(s). IEEE Micro, 43 (5): 88-96 (September 2023)