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Disambiguation of "Bhattacharyya, Shuvra S."

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Intermediate Representations for Design Automation of Multiprocessor DSP Systems.

, , , and . Des. Autom. Embed. Syst., 7 (4): 307-323 (2002)

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Somnath Bhattacharyya

Abinaschchandra Bhattacharyya

Arnab Bhattacharyya

Rameswar Bhattacharyya

Jyotirmay Bhattacharyya

 

Other publications of authors with the same name

Toward Efficient Many-core Scheduling of Partial Expansion Graphs., , , and . SCOPES, page 100-103. ACM, (2018)Partial expansion of dataflow graphs for resource-aware scheduling of multicore signal processing systems., , , and . ACSSC, page 385-392. IEEE, (2014)Constant-rate clock recovery and jitter measurement on deep memory waveforms using dataflow., , and . I2MTC, page 1590-1595. IEEE, (2015)The hierarchical timing pair model for multirate DSP applications., , and . IEEE Trans. Signal Process., 52 (5): 1209-1217 (2004)Memory management for dataflow programming of multirate signal processing algorithms., and . IEEE Trans. Signal Process., 42 (5): 1190-1201 (1994)Communication strategies for shared-bus embedded multiprocessors., and . EMSOFT, page 21-24. ACM, (2005)Guest Editorial., , and . VLSI Signal Processing, 40 (1): 5-6 (2005)Prinet: A Prior Driven Spectral Super-Resolution Network., , , and . ICME, page 1-6. IEEE, (2020)A design tool for high performance image processing on multicore platforms., , , and . DATE, page 1304-1309. IEEE, (2018)Reconfigurable Digital Channelizer Design Using Factored Markov Decision Processes., , , , and . J. Signal Process. Syst., 90 (10): 1329-1343 (2018)